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1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ugate1 vcc ugate2 phase2 pg ood ocset2 fb2 v5 ss fault/rt phase1 lgate1 pg nd ocset1 vse n1 fb1 fb3 gate gnd v3.3 ? vga card power regulation ? ? ? ? ? 3 regulated voltage are provided ? ? ? ? ? sync switching power for vtt(1.25v) ? ? ? ? ? async switching power for nvvdd(2.05v) ? ? ? ? ? linear regulator for fbvddq(2.5v) ? ? ? ? ? simple single-loop control design ? ? ? ? ? voltage-mode pwm control ? ? ? ? ? excellent output voltage regulation ? ? ? ? ? vtt output : : : : : 1% over temperature ? ? ? ? ? nvvdd output : : : : : 2% over temperature ? ? ? ? ? fbvddq output:2.5% over temperature ? ? ? ? ? fast transient response ? ? ? ? ? on-chip feedback compensation ? ? ? ? ? full 0% to 100% duty ratio ? ? ? ? ? power-good output voltage monitor ? ? ? ? ? over-voltage and over-current fault monitors ? ? ? ? ? small converter size ? ? ? ? ? constant frequency operation(200khz) ? ? ? ? ? programmable oscillator from 50khz to 800khz ? ? ? ? ? reduce external component count

the APW7026 provides the power control and protection for three output voltages in vga card applications. it integrates two pwm controllers, one linear controller as well as the monitoring and protection functions into a single package. one pwm controller (pwm1) regulates the termination voltage vtt(1.25v) with a synchronous-rectified buck converter. the second pwm controller (pwm2) supplies the core power nvvdd ( 2.05v ) with a standard buck converter . the linear controller regulates 2.5v power for fbvddq. the APW7026 can monitor all the output voltages (vtt ,nvvdd,fbvddq) and a single power good signal is issued when the vtt is within 10% of the reference voltage (v ref1 ) and the other levels are above its lower power good threshold voltage. additional built-in overvoltage protection (ovp) will be started when the vtt output is above 118% of the v ref1. the ovp function will shutdown the upper mosfet and turn on the lower mosfet until the over-voltage is disappeared. the pwm controllers over-current function monitors the out- put current by sensing the voltage drop across the upper mosfet r ds(on) , eliminating the need for a current sensing resistor.

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symbol parameter rating unit vcc supply voltage 15 v v i , v o input , output or i/o voltage gnd -0.3 v to vcc +0.3 v t a operating ambient temperature range 0 to 70 o c t j junction temperature range 0 to 125 o c t stg storage temperature range -65 to +150 o c t s soldering temperature 300 ,10 seconds o c apw 7026 voltage code 12 : 1.25v package code k : so p - 20 temp. range c : 0 to 70 c handling code tu : tube tr : tape & reel lead free code l : lead free d evice blank : o riginal d evice handling code temp. range package code voltage code lead free code gate control soft-start and fault logic thermal protection gate control power-on reset fb3 gate ocset2 ugate2 phase2 fb2 v3.3 gnd pgnd lgate1 phase1 ugate1 pgood v5 vcc ocset1 vsen1 fb1 ss fault/rt 0.3v v ref3 1.26v 200ua vcc drive2 oc2 inhibit pwm2 v ref2 2.0v error amp2 2.5v 4.1v 5v oscillator 23k 4.6v v ref1 error amp1 0v fault oc1 pwm1 vcc low er drive vcc drive1 inhibit 118% 90% 110% 200ua luv

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symbol parameter value unit r ja thermal resistance in free air soic soic (with 3in 2 of copper) 75 65 o c 1. recommended operating conditions, unless otherwise noted. 2. refer to block and simplified power system diagrams , and typical application schematic. APW7026 unit symbol parameter test conditions min typ max supply current i cc nominal supply current ugate1, lgate1, ugate2, and gate open 6ma power-on reset rising vcc threshold 9.5 10.4 v falling vcc threshold 8.2 9.0 v rising v5 threshold 4.4 4.7 v falling v5 threshold 3.7 4.0 v oscillator f osc free running frequency rt = open 185 200 215 khz ? v osc ramp amplitude rt = open 1.9 v pwm controller reference voltage v ref1 sync pwm controller reference voltage 1.25 v v ref1 accuracy -1 +1 % v ref2 async pwm controller reference voltage 2.0 v v ref2 accuracy -2 +2 % linear controller v ref3 reference voltage gate=fb3 1.26 v v ref3 accuracy -2.5 +2.5 % gate drive current v gate =4v 20 50 ma pwm controllers gate drivers i ugate ugate1,2 source vcc = 12v, v ugate1 (or v ugate2 ) = 6v 1.0 a r ugate ugate1,2 sink vcc = 12v, v ugate1 (or v ugate2 ) = 1v 2.2 3.5 ? i lgate lgate1 source vcc = 12v, v lgate1 = 1v 1.0 a r lgate lgate1 sink vcc = 12v, v lgate1 = 1v 1.6 3.0 ?

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1. recommended operating conditions, unless otherwise noted. 2. refer to block and simplified power system diagrams , and typical application schematic. apw 7026 unit sym bol param eter test conditions min typ max protection vsen1 o .v. trip point (vsen1/v ref1 ) vsen 1 rising 11 8 % vsen1 o .v. hysteresis 2% v3.3 o .v. trip point v3.3 rising 4.1 v v3.3 o .v. hysteresis 0.1 v l ovp fault souring current v fau lt/rt = 2.0v 25 m a o cset 1,2 current source vocset = 4.5v 170 200 230 ua r ss pull up resistor to 5v 23 k ? power good vsen1 upper threshold (v s e n 1/v ref1 ) vsen1 rising 110 % vsen 1 lower threshold vsen1 rising 94 % vsen1 pg d hysteresis upper/lower threshold 2 % v3.3 lower threshold v3.3 rising 2.5 v v3.3 pgd hysteresis 0.1 v fb3 lower threshold v fb3 rising 1.0 v fb3 pg d hysteresis 0.1 v v pgood pgood voltage low l pgood = -4m a 0.8 v ugate1 (pin 1) connect ugate1 pin to the sync pwm converter?s upper mosfet gate .this pin provides the gate drive for the upper mosfet. vcc (pin 2) provide a + 12v bias supply for the ic to this pin . this pin also provides the gate bias charge for all the mosfets controlled by the ic. the voltage at this pin is monitored for power-on reset (por) purpose. ugate2 (pin 3) connect ugate2 pin to the async pwm converter?s mosfet gate . this pin provides the gate drive for the mosfet. phase2 (pin 4) connect the phase2 pin to the async pwm converter?s mosfet source. this pin is used to monitor the voltage drop across the mosfet for over-current protection. pgood (pin 5) pgood is an open drain output used to indicate the status of the output voltages. this pin is pulled low when the sync pwm regulator output is not within 10% of the reference voltage (v ref1 ) or when v3.3 or v fb3 is below its lower power good threshold. ocset2 (pin 6) connect a resistor (r ocset ) from this pin to the drain of the async pwm converter?s mosfet . r ocset , an internal 200 a current source (i ocset ) , and the mosfet?s on-resistance (r ds(on) ) set the converter?s over-current (oc) trip point according to the following equation: i peak = an over-current trip cycles the soft-start function. fb2 (pin 7) connect this pin to the output of the async pwm converter . the voltage at this pin is regulated to the reference voltage v ref2 . a resistor driver is connected from this pin to v out2 (r out2 ) and to gnd(r gnd2 ) that sets the output voltage as the following equation : i ocset x r ocs et r ds(on)

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+ functional pin description cont. v out2 = the value of the resistor connected from v out2 to fb2 must be less than 150 ? . v5 (pin 8) the +5v input voltage at this pin is monitored for power-on reset (por) purpose. ss (pin 9) this pin provides the soft-start for the all pwm converters and linear regulator . an internal resistor charges an external capacitor that is connected from 5v supply to this pin which ramps up the all outputs , preventing the outputs from overshooting as well as limiting the input current . the second function of the soft-start cap is to provides long off time for the synchronous mosfet during current limiting . fault / rt (pin 10) this pin provides oscillator switching frequency adjustment . by placing a resistor ( r t ) from this pin to gnd , the nominal 200khz switching frequency is increased .conversely, connecting a pull-up resistor ( r t ) from this pin to vcc reduces the switching frequency. nominally , the voltage at this pin is 1.26v. in the event of an over-voltage or over-current condition , this pin is internally pulled to vcc. v3.3 (pin 11) this pin is connected to the +3.3v or the output of the async pwm converter for power good and over-voltage detection. when the output voltage of the async pwm converter is not in the range from 3v to 4v, connect this pin to +3.3v voltage. gnd (pin 12) signal ground for the ic. all voltage levels are measured with respect to this pin. gate (pin 13) connect this pin to the gate of an external mosfet. this pin provides the drive for the linear regulator ? s r out2 r gnd2 ( 1+ ) x v ref2 pass mosfet . fb3 (pin 14) connect this pin to the output of the linear regulator . a resistor driver is connected from this pin to v out3 and gnd that sets the output voltage as same as v out2 . this pin is monitored for power good function. fb1 (pin 15) this pin provides the feedback for the sync pwm converter. typically this pin can be connected directly to the output of the converter . however , a resistor divider is recommended to be connected from this pin to v out1 and gnd to adjust the output voltage as same as v out2 . the value of the resistor connected from v out1 to fb1 must be less than 200 ? . vsen1 (pin 16) this pin is connected to the sync pwm converter ? s output voltage . the pgood and ovp comparator cicuits use this signal to report output voltage status and over-voltage protection. ocset1 (pin 17) connect a resistor (r ocset ) from this pin to the drain of the sync pwm converter ? s upper mosfet . the over-current (oc) trip point for the sync pwm converter is set by the r ocset as same as the ocset2. an over-current trip cycles the soft-start function. pgnd (pin 18) this is the power ground connection . tie the sync pwm converter ? s lower mosfet source to this pin. lgate1 (pin 19) connect lgate1 to the sync pwm converter ? s lower mosfet gate . this pin provides the gate drive for the lower mosfet. phase1 (pin 20) connect the phase1 pin to the sync pwm converter ? s upper mosfet source. this pin is used to monitor the voltage drop across the upper mosfet for over-current protection.

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, typical performance curves 1 10 100 1000 10000 50 150 250 350 450 550 650 750 switching frequency ( khz ) -1.0% -0.8% -0.6% -0.4% -0.2% 0.0% 0.2% 0.4% 0.6% 0.8% 1.0% 0255075100125 reference voltage deviation(v ref1 ) junction temperature ( o c) -1.0% -0.8% -0.6% -0.4% -0.2% 0.0% 0.2% 0.4% 0.6% 0.8% 1.0% 0255075100125 reference voltage deviation(v ref2 ) junction temperature ( o c) -1.0% -0.8% -0.6% -0.4% -0.2% 0.0% 0.2% 0.4% 0.6% 0.8% 1.0% 0255075100125 note : the referance voltage(v ref ) deviation is junction temperature ( o c) v ref (t j ) - v ref (25 o c) v ref (25 o c) x 100% rt ( k ? ) rt pull up to +12v rt pull down to g nd reference voltage deviation(v ref1 ) r r r r r t t t t t t j is junction temperature.

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- typical application circuit ugate1 pgood phase2 ugate2 vcc ss fb2 ocset2 v5 fb3 vsen1 fb1 gate lgate1 pgnd ocset1 phase1 1 7 6 5 4 3 2 13 14 15 16 17 18 19 20 12 11 +5v nvvdd 2.05v/4a vtt 1.25v/3.5a agp 3.3v +12v agp 3.3v fbvddq 2.5v/1.5a c807 330uf c808 330uf r812 1.5k c809 220pf r813 5.1r q802 apm9410 d800 fm5820 c811 330uf r814 100rf c810 330uf r810 97.6rf c817 330uf q800 apm3055 c802 330uf r820 5.1r q803b apm7313 c815 330uf c816 330uf c814 10uf c813 330uf l802 2uh l803 7.8uh q803a apm7313 c812 220pf r817 1.2k r819 5.1r c801 1uf rx1 10r l801 7.8uh l800 2uh APW7026-12 r811 100rf 10 9 8 5v c805 1uf r816 4.02kf fault/rt gnd v3.3 r821 0r r824 nc simplified power system diagram v out1 q1 q2 q3 q4 v out3 +3.3v async pwm controller linear controller sync pwm controller +3.3v v out2 +5v

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so ? 300mil ( reference jedec registration ms-013) millimeters variations- d inches variations- d dim min. max. variations min. max. dim min. max. variations min. max. a2.35 2.65 so-16 10.10 10.50 a 0.093 0.1043 so-16 0.398 0.413 a1 0.10 0.30 so-18 11.35 11.76 a1 0.004 0.0120 so-18 0.447 0.463 b 0.33 0.51 so-20 12.60 13 b 0.013 0.020 so-20 0.496 0.512 d see variations so-24 15.20 15.60 d see variations so-24 0.599 0.614 e 7.40 7.60 so-28 17.70 18.11 e 0.2914 0.2992 so-28 0.697 0.713 e1.27bscso-14 8.80 9.20 e 0.050bsc so-14 0.347 0.362 h 10 10.65 h0.3940.419 l 0.40 1.27 l0.0160.050 n see variations n see variations 10 8 10 8 n 12 3 e h d l gauge plane 1 e b a1 a

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t 25 c to peak tp ramp-up t l ramp-down ts preheat tsmax tsmin t l t p 25 temperature time critical zone t l to t p terminal material solder-plated copper (solder material : 90/10 or 63/37 snpb), 100%sn lead solderability meets eia specification rsi86-91, ansi/j-std-002 category 3. " +$!

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sn-pb eutectic assembly pb-free assembly profile feature large body small body large body small body average ramp-up rate (t l to t p ) 3 c/second max. 3 c/second max. preheat temperature min (tsmin) temperature mix (tsmax) time (min to max)(ts) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds tsmax to t l - ramp-up rate 3 c/second max tsmax to t l temperature(t l ) time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(tp) 225 +0/-5 c 240 +0/-5 c 245 +0/-5 c 250 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 10-30 seconds 10-30 seconds 20-40 seconds ramp-down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note: all temperatures refer to topside of the package. measured on the body surface.

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) test item method description solderability mil-std-883d-2003 245 c , 5 sec holt mil-std-883d-1005.7 1000 hrs bias @ 125 c pct jesd-22-b, a102 168 hrs, 100 % rh , 121 c tst mil-std-883d-1011.9 -65 c ~ 150 c, 200 cycles esd mil-std-883d-3015.7 vhbm > 2kv, vmm > 200v latch-up jesd 78 10ms , i tr > 100ma t ao e w po p ko bo d1 d f p1 a j b t2 t1 c application a b c j t1 t2 w p e sop- 28 330 1 62 1.5 12.75 0. 5 2 0.6 24.4 0.2 2 0.2 24 0.3 12 0.1 1.75 0.1 application f d d1 po p1 ao bo ko t sop- 28 11.5 0.1 1.5 +0.1 1.5+ 0.25 4.0 0.1 2.0 0.1 10.85 0.1 18.34 0.1 2.97 0.1 0.35 0.01 (mm)

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anpec electronics corp. head office : 5f, no. 2 li-hsin road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 7f, no. 137, lane 235, pac chiao rd., hsin tien city, taipei hsien, taiwan, r. o. c. tel : 886-2-89191368 fax : 886-2-89191369 $-&

application carrier width cover tape width devices per reel sop- 28 24 21.3 1000

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